UART Initialization & Configuration

The following steps show how to initialize the UART peripheral.

1. Enable Clock to the UART Modules (RCGCUART register)
   The first step to configuring UART is to control the clocking for the UART modules. When enabled a UART module is provided a clock and access to module registers is allowed. When disabled, the clock is disabled to save power, and access to module registers generates a bus fault.
   
   • 0: UART module is disabled
   • 1: Enable and provide a clock to the UART module in RUN mode
   
   

   	8	4	2	1		8	4	2	1
   	7	6	5	4		3	2	1	0	bit
   RCGCUART	UART Module 7	UART Module 6	UART Module 5	UART Module 4		UART Module 3	UART Module 2	UART Module 1	UART Module 0	UART
   					-

   SYSCTL->RCGCUART = _MyDefines.h
   
   After enabling the clock signal, check the PRUART register until the corresponding bit is set to 1.
   In C:
   while ( (SYSCTL->PRUART & (__) ) != (__)) {};
   
   
2. UART Control Register
   
   
   The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register:
   

   1. Disable the UART.
   2. Wait for the end of the transmission or reception of the current character.
   3. Flush the transmit FIFO by clearing bit 4 (FEN) in the UARTLCRH register.
   4. Reprogram the UARTCTL register.
   5. Enable the UART
   
   

   Bit/Field	Name	Value	Description
   15	CTSEN		Enable CTS (Clear To Send)
   		0	CTS hardware flow control is disabled
   		1	CTS hardware flow control is enabled
   14	RTSEN		Enable RTS (Request To Send)
   		0	RTS hardware flow control is disabled
   		1	RTS hardware flow control is enabled
   11	RTS		The status of RTS signal (If RTSEN is set, this bit is ignored)
   9	RXE		UART RX (Receive) Enable
   		0	The RX is disabled
   		1	The RX is enabled
   8	TXE		UART TX (Transmit) Enable
   		0	The TX is disabled
   		1	The TX is enabled
   7	LBE		UART Loop Back Enable
   		0	Normal operation.
   		1	The UnTX path is fed through the UnRX path.
   5	HSE		High-Speed Enable
   		0	The UART is clocking using the system clock divided by 16
   		1	The UART is clocking using the system clock divided by 8

   Bit/Field	Name	Value	Description
   4	EOT		End of Transmission. This bit determines the behavior of the TXRIS bit in the UARTRIS register
   		0	The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met
   		1	The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer
   3	SMART		ISO 7816 Smart Card Support
   		0	Normal operation
   		1	The UART operates in Smart Card mode
   2	SIRLP		UART SIR Low-Power Mode
   		0	Low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period
   		1	The UART operates in SIR Low-Power mode.
   1	SIREN		UART SIR Enable
   		0	Normal operation
   		1	The IrDA SIR block is enabled.
   0	UARTEN		UART Enable
   		0	The UART is disabled.
   		1	The UART is enabled.

   
   

   	8	4	2	1		8	4	2	1		8	4	2	1		8	4	2	1
   	15	14	13	12		11	10	9	8		7	6	5	4		3	2	1	0	bit
   UARTCTL	CTSEN	RTSEN				RTS		RXE	TXE		LBE		HSE	EOT		SMART	SIRLP	SIREN	UARTEN
   			0	0	-		0			-		0			-

   
   UART->CTL = _MyDefines.h
   
   
   
3. Baud-Rate Divisor (BRD)
   A baud-rate divisor is a 22-bit number consisting of a 16-bit integer (UARTIBRD) and a 6-bit fractional part (UARTFBRD).
   

   The UARTLCRH register, the UARTIBRD and UARTFBRD registers are connected to an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed. So, any changes to the baud-rate divisor (UARTIBRD and/or UARTFBRD) must be followed by a write to the UARTLCRH register for the changes to take effect.

   
   There are four possible sequences to update the baud-rate registers:
   
   • UARTIBRD write, UARTFBRD write, and UARTLCRH write
   • UARTFBRD write, UARTIBRD write, and UARTLCRH write
   • UARTIBRD write and UARTLCRH write
   • UARTFBRD write and UARTLCRH write
   
   

   	31 ~ 16	15 ~ 0	bit
   UARTIBRD		DIVINT	UART
   	0

   UART ->IBRD = decimal
   

   	31 ~ 4	5 ~ 0	bit
   UARTFBRD		DIVFRAC	UART
   	0

   UART ->FBRD = _decimal
   
   
   1. UART Line Control, High Byte (UARTLCRH)
      The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop-bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.
      

      Bit/Field	Name	Value	Description
      7	SPS		UART Stick Parity Select
      		0	Stick parity is disabled
      		1	When bits 1, 2, and 7 are set, the parity bit is transmitted and checked as a 0 When bits 1 and 7 are set, and bit 2 is cleared, the parity bit is transmitted and checked as a 1.
      6:5	WKEN		UART Word Length
      		0x0	5 bits (default)
      		0x1	6 bits
      		0x2	7 bits
      		0x8	8 bits
      4	FEN		UART Enable FIFOs
      		0	The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
      		1	The transmit and receive FIFO buffers are enabled (FIFO mode).
      3	STP2		UART Two Stop Bits Select
      		0	One stop bit is transmitted at the end of a frame
      		1	Two stop bits are transmitted at the end of a frame
      2	EPS		UART Even Parity Select. (This bit has no effect when parity is disabled by the PEN bit)
      		0	Odd parity is performed, which checks for an odd number of 1s
      		1	Even parity generation and checking are performed during transmission and reception, which checks for an even number of 1s in data and parity bits
      1	PEN		UART Parity Enable
      		0	Parity is disabled, and no parity bit is added to the data frame
      		1	Parity checking and generation are enabled
      0	BRK		UART Send Break
      		0	Normal use
      		1	After transmitting the current character, a low level is continually outputted on the UnTxsignal. For the proper execution of the break command, the software must set this bit for at least two frames (character periods).

      -----
      

      	8	4	2	1		8	4	2	1
      	7	6	5	4		3	2	1	0	bit
      UARTCTL	SPS	WLEN		FEN		STP2	EPS	PEN	BRK
      					-

      UART ->LCRH = _MyDefines.h
4. Baud Clock Source for UART Module
   

   If the PIOSC is used for the UART baud clock, the system clock frequency must be at least 9 MHz in Run mode.

   TM4C123G

   TM4C1294

5. UART Flag (UARTFR)
   The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. The CTS bit indicates the modem flow control.
   Note that modem control and status bits (RI, DCD, and DSR bits) are applicable to specific UART modules on the TM4C microcontrollers as follows:
   
   • TM4C123G Board:
     • Modem control bits are only implemented on UART1. For UART0 and UART2, these bits are reserved and not functional.
   • TM4C1294 Board:
     • UART0 and UART1 support both modem flow control and modem status.
     • UART2, UART3, and UART4 support modem flow control only.
   
   
   

   Bit/Field	Name	Value	Description
   8	RI		Ring Indicator
   		0	The UnRI signal is not asserted.
   		1	The UnRI signal is asserted.
   7	TXFE		UART Transmit FIFO Empty
   		0	The transmitter has data to transmit.
   		1	If the FIFO is disabled (FEN is 0), the transmit holding register is empty. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.
   6	RXFF		UART Receive FIFO Full
   		0	The receiver can receive data.
   		1	If the FIFO is disabled (FEN is 0), the receive holding register is full. If the FIFO is enabled (FEN is 1), the received FIFO is full.
   5	TXFF		UART Transmit FIFO Full
   		0	The receiver is not empty.
   		1	If the FIFO is disabled (FENis 0), the transmit holding register is full. If the FIFO is enabled (FENis 1), the transmit FIFO is full.
   4	RXFE		UART Receive FIFO Empty
   		0	The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.
   		1	If the FIFO is disabled (FENis 0), the receive holding register is empty. If the FIFO is enabled (FENis 1), the received FIFO is empty.
   3	BUSY		UART Busy
   		0	The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register.
   		1	Two stop bits are transmitted at the end of a frame
   2	DCD		Data Carrier Detect
   		0	The UnDCD signal is not asserted
   		1	The UnDCD signal is asserted
   1	DSR		Data Set Ready
   		0	The UnDSR signal is not asserted
   		1	The UnDSR signal is asserted
   0	CTS		Clear To Send
   		0	The U1CTS signal is not asserted
   		1	The U1CTS signal is asserted

   -----
   

   	1		8	4	2	1		8	4	2	1
   	8		7	6	5	4	3	2	1	0	bit
   UARTFRL	RI		TXFE	RXFF	TXFF	RXFE		BUSY	DCD	DSR	CTS
   		-					-

6. UART Data (UARTDR)
   This register serves as the data interface to the UART FIFOs.
   
   • For Transmission:
     • If the FIFO is enabled, any data written to this register is pushed onto the transmit FIFO.
     • If the FIFO is disabled, the data is placed in the transmitter holding register (the first position of the transmit FIFO).
     • Writing to this register initiates a transmission from the UART.
   • For Reception:>
     • If the FIFO is enabled, each received data byte, along with its 4-bit status (indicating break, frame, parity, and overrun errors), is pushed onto the 12-bit wide receive FIFO.
     • If the FIFO is disabled, the data byte and its status are stored in the receiver holding register (the first position of the receive FIFO).
     • Received data can be accessed by reading from this register.
   ----
   

   Bit/Field	Name	Value	Description
   11	OE		UART Overrun Error
   		0	No data has been lost due to a FIFO overrun.
   		1	New data was received when the FIFO was full, resulting in a data loss.
   10	BE		UART Break Error
   		0	No break condition has occurred.
   		1	A break condition has been detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
   9	PE		UART Parity Error
   		0	No parity error has occurred.
   		1	The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.
   8	FE		UART Framing Error
   		0	No framing error has occurred.
   		1	The received character does not have a valid stop bit (a valid stop bit is 1).
   7:0	DATA		Data Transmitted or Received
   			Data to be transmitted via the UART is written to this field. When read, this field contains the data received by the UART.