PWM Initialization & Configuration

Find the frequency of the system clock, and calculate the frequency of the PWM Timer.

System Clock
SysClk (Hz)		 PWMDIV fPWMTimer = SysClk / PWMDIV
(Hz)

Check the PCTL table (for 123G or 1294) to find the pins which support PWM peripheral signal

GPIO
Port.Pin		 PWM
Module		 PCTL PWM
Module
(m)		 Generator
(n)		 Signal GEN Output Signal Type Output
Frequency
fPWM
 LOAD
Value
(16-bit)		 Initial
CMP
Value
(16-bit)

You have to know the frequency of the System Clock (1), the frequency of PWM output signal (2), and the initial value for duty cycle (3). Then, calculate the LOAD value and CMP value.

\(LOA{D_{16bit}} = \frac{{{f_{PWMTimer}}}}{{{f_{PWM}}}}\)

For Left-Aligned PWM Signals

Calculate CMP value by duty cycle (%):

\(CM{P_{16bit}} = LOAD \times (1 - Dut{y_\% }) = \frac{{{f_{PWMTimer}}}}{{{f_{PWM}}}} \times (1 - Dut{y_\% })\)

Calculate CMP value by pulse width:

\(CM{P_{16bit}} = LOAD - \frac{{{T_{PulseWidth}}}}{{{T_{PWMTimer}}}} = ({T_{PWM}} - {T_{PulseWidth}}) \times {f_{PWMTimer}}\)

For Right-Aligned PWM Signals

Calculate CMP value by duty cycle (%):

\(CM{P_{16bit}} = LOAD \times Dut{y_\% } = \frac{{{f_{PWMTimer}}}}{{{f_{PWM}}}} \times Dut{y_\% }\)

Calculate CMP value by pulse width:

\(CM{P_{16bit}} = \frac{{{T_{PulseWidth}}}}{{{T_{PWMTimer}}}} = {T_{PulseWidth}} \times {f_{PWMTimer}}\)

The following steps show how to initialize PWM peripheral.

      1. Enable Clock to the PWM Modules (RCGCPWM register)
        TM4C123G:
        8 4 2 1 8 4 2 1
        7 6 5 4 3 2 1 0 bit
        PWM
        Module 1        		 PWM
        Module 0        		 PWM
        0 0 0 0 - 0 0
        SYSCTL->RCGCPWM = MyDefines.h
        = binary = hex

        TM4C1294:
        8 4 2 1 8 4 2 1
        7 6 5 4 3 2 1 0 bit
        PWM
        Module 0        		 PWM
        0 0 0 0 - 0 0 0
        SYSCTL->RCGCPWM = MyDefines.h
        = binary = hex


        After enable clock signal, check the PRPWM register until the corresponding bit set to 1.
        In C:
        while ( (SYSCTL->PRPWM & (__) ) != (____ )) {};
      2. Enable and Setup Clock Divider for all PWM modules
        USEPWMDIV: Enable PWM Clock Divisor
        • 0: The system clock is the source for the PWM clock
        • 1: The PWM clock divider is the source for the PWM clock

        PWMDIV: PWM Unit Cloxk Divisor
        • 0x0: /2
        • 0x1: /4
        • 0x2: /8
        • 0x3: /16
        • 0x4: /32
        • 0x5: /64

        TM4C123G:
        RCC 31 ~ 21 20 19 ~ 17 16 ~ 0 bit
        USEPWMDIV PWMDIV
        x x
        SYSCTL->RCC &= ~(0x7 << 17); // RCC[19:17]=000 PWMDIV
        SYSCTL->RCC |=
        |= |=

        TM4C1294:
        PWMCC 31 ~ 9 8 7 ~ 3 2 ~ 0 bit
        USEPWMDIV PWMDIV
        x x
        PWM0->CC &= ~(0x7); // PWMCC[2:0]=000 PWMDIV
        PWM0->CC |=
        |= |=

      3. PWM Signal Generation Control Register (PWMnCTL)
        MODE: Counter Mode
        • 0: Count-Down mode
        • 1: Count-Up/Down mode

        ENABLE: PWM Block Enable
        • 0: The entire PWM generation block is disable and not not clocked
        • 1: The PWM generation block is enabled and produces PWM signals
        PWMnCTL 31 ~ 19 18 17 16 15 ~ 14 13 ~ 12 11 ~ 10 9 ~ 8 bit
        LATCH MINFLTPER FLTSRC DBFALLUPD DBRISEUPD DBCTLUPD GENBUPD
        x
        PWMnCTL 7 ~ 6 5 4 3 2 1 0 bit
        GENAUPD CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE

        PWM ->_ _CTL =
        = =

      4. Setup the Period of the PWM Signal (PWMnLOAD)
        The 16-bit LOAD value is used to control the PWM period.
        PWMnLOAD 31 ~ 16 15 ~ 0 bit
        LOAD

        PWM ->_ _LOAD =

      5. Setup the Initial Duty Cycle (PWMnCMPA / PWMnCMPB)
        The PWMnCMPA / PWMnCMPB registers are used to compare against the PWM counter. When this value matches the counter, a pulse is output which can be configured to drive the pwmA and pwmB signals (via the PWMnGENA and PWMnGENB).
        PWMnCMPA 31 ~ 16 15 ~ 0 bit
        CMPA

        PWM ->_ _CMPA =

        PWMnCMPB 31 ~ 16 15 ~ 0 bit
        CMPB

        PWM ->_ _CMPB =

      6. Setup PWM Signal Type (PWMnGENA / PWMnGENB)
        These register control the generation of the pwmA/pwmB signal based on the load and zero output pulses from the counter, as well as the compare A (CMPA) and compare B (CMPB) pulses from the comparators.
          • 0x0: Do nothing
          • 0x1: Invert PWM signal
          • 0x2: Drive PWM signal Low
          • 0x3: Drive PWM signal High

        ACTCMPBD: Action for Comparator B in count-down mode
        ACTCMPBU: Action for Comparator B in count-up mode
        ACTCMPAD: Action for Comparator A in count-down mode
        ACTCMPAU: Action for Comparator A in count-up mode
        ACTLOAD: Action for Counter = LOAD
        ACTZERO: Action for Counter = 0


        Counter running in Count-Down mode
        PWMnGENA/B 31 ~ 12 11 ~ 10 9 ~ 8 7 ~ 6 5 ~ 4 3 ~ 2 0 ~ 1 bit
        ACTCMPBD ACTCMPBU ACTCMPAD ACTCMPAU ACTLOAD ATZERO
        x

        PWM ->_ _GENA =
        = =

        PWM ->_ _GENB =
        = =


        Counter running in Count-Up/Down mode
        PWMnGENA/B 31 ~ 12 11 ~ 10 9 ~ 8 7 ~ 6 5 ~ 4 3 ~ 2 0 ~ 1 bit
        ACTCMPBD ACTCMPBU ACTCMPAD ACTCMPAU ACTLOAD ATZERO

        PWM ->_ _GENA =
        = =

        PWM ->_ _GENB =
        = =

      7. PWM Output Enable (PWMnENABLE)
        This register provides a master control of which PWM signals are output to the GPIO pins. By disabling a PWM output, the PWM generation process can continue without driving PWM signals to the pins.
        • 0: The PWM signal has a zero value
        • 1: The generated PWM signal is passed to the GPIO pin
        8 4 2 1 8 4 2 1
        7 6 5 4 3 2 1 0 bit
        PWM Module PWM
        7        		 PWM
        6        		 PWM
        5        		 PWM
        4        		 - PWM
        3        		 PWM
        2        		 PWM
        1        		 PWM
        0        		 pin Value in Hex Register Value to Register
        - - = ➤ PWM ->ENABLE
        - - = ➤ PWM ->ENABLE

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