Lesson 10: Reset, Registers, and Counters in Verilog

Flip-Flop (FF) — the physical primitive provided by the FPGA fabric. A single-bit storage cell clocked by the system clock.

Register — one or more flip-flops grouped together to store a multi-bit value, usually sharing a common clock and reset signal.

Counter — a register augmented with combinational feedback logic (an adder or subtractor) that modifies its own value on each clock cycle.

Reset — a mechanism applied at the flip-flop level that initializes all registers and counters to a known state at startup or on demand.

Rule 1: Use asynchronous reset for control logic; use synchronous reset for datapath logic.
Control modules (FSMs, protocol controllers) must recover to a safe state under any condition, including clock failure. Datapath modules only require initialization at startup, and synchronous reset produces cleaner timing analysis results.

Rule 2: Always pair asynchronous reset with a Reset Synchronizer.
The industry-standard pattern is "asynchronous assert, synchronous deassert." This preserves the immediate clearing capability of the asynchronous reset while guaranteeing stable, glitch-free deassertion synchronized to the clock.

Rule 3: Use active-low reset consistently throughout the entire design.
The naming convention rst_n is the industry standard. The hardware CLR pin of the Intel MAX-10 flip-flop is also active-low. Maintaining this convention throughout the design eliminates polarity confusion errors.

Rule 4: Verify that the reset pulse width meets device specifications.
A synchronous reset pulse must be wider than one clock period. An asynchronous reset pulse must meet the flip-flop's minimum CLR pulse width requirement. Both values can be found in the Intel MAX-10 Device Handbook.

A reset signal can be designed to assert on a logic low (active-low, rst_n = 0 triggers reset) or on a logic high (active-high, rst = 1 triggers reset). Both are functionally valid, but the industry standard — and the recommendation for this course — is active-low reset for the following reasons:

• Hardware alignment: The dedicated CLR pin of the Intel MAX-10 flip-flop is natively active-low. Using active-low reset in RTL maps directly to this hardware pin without requiring an inverter, saving logic resources and avoiding additional propagation delay.
• Fail-safe behavior: An undriven or floating reset line defaults to logic low (0), asserting the reset and holding the system in a safe, initialized state. With an active-high reset, a floating line would release the reset and allow the system to run from an undefined state.
• Industry convention: The naming suffix _n (e.g., rst_n, nreset) is universally recognized as an active-low signal. Most commercial IP cores, AMBA bus interfaces, and reference designs follow this convention.

The following example demonstrates both polarities side by side. Note that the only difference is the condition used to check the reset state:

// Active-low reset (recommended)
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)          // Reset is active when rst_n = 0
        q <= 8'h00;
    else
        q <= d;
end

// Active-high reset (avoid unless required by IP interface)
always @(posedge clk or posedge rst) begin
    if (rst)             // Reset is active when rst = 1
        q <= 8'h00;
    else
        q <= d;
end

Design rule: adopt active-low reset as the project-wide standard. If an external IP core uses active-high reset at its interface, add a single inversion at the boundary rather than changing the internal reset polarity of your design.

As established in Section 10.2.4, asynchronous reset deassertion can cause metastability if it occurs too close to a clock edge. The solution is a Reset Synchronizer that implements the industry-standard pattern of asynchronous assert and synchronous deassert.

Why Two Stages?

// Standard two-stage Reset Synchronizer
// Place one instance per clock domain in the design
module reset_synchronizer (
    input  wire clk,
    input  wire async_rst_n,   // Raw asynchronous reset input
    output wire sync_rst_n     // Synchronized reset output for this clock domain
);
    // Declare as registers with no initial value — reset handles initialization
    reg stage1_ff;
    reg stage2_ff;

    always @(posedge clk or negedge async_rst_n) begin
        if (!async_rst_n) begin
            stage1_ff <= 1'b0;   // Asynchronous assert: both stages clear immediately
            stage2_ff <= 1'b0;
        end else begin
            stage1_ff <= 1'b1;          // Deassert propagates through stage 1
            stage2_ff <= stage1_ff;     // Then through stage 2 on next cycle
        end
    end

    assign sync_rst_n = stage2_ff;
endmodule

Multi-Clock-Domain Reset Distribution

// Top-level reset distribution for a two-clock-domain design
module top (
    input wire clk_50m,
    input wire clk_100m,
    input wire ext_rst_n     // Single external reset button
);
    wire rst_n_50m;    // Synchronized reset for the 50 MHz domain
    wire rst_n_100m;   // Synchronized reset for the 100 MHz domain

    // Independent synchronizer for each clock domain
    reset_synchronizer u_rst_sync_50m (
        .clk         (clk_50m),
        .async_rst_n (ext_rst_n),
        .sync_rst_n  (rst_n_50m)
    );

    reset_synchronizer u_rst_sync_100m (
        .clk         (clk_100m),
        .async_rst_n (ext_rst_n),
        .sync_rst_n  (rst_n_100m)
    );

    // Each sub-module receives the reset synchronized to its own clock domain
    // uart_ctrl u_uart (.clk(clk_50m),  .rst_n(rst_n_50m),  ...);
    // dsp_core  u_dsp  (.clk(clk_100m), .rst_n(rst_n_100m), ...);

endmodule

A reset signal that must drive hundreds or thousands of flip-flops simultaneously creates a high-fan-out net. If this net is routed through the standard interconnect fabric, the routing delay can become so large that some flip-flops receive the reset signal significantly later than others — violating timing and potentially causing inconsistent reset behavior across the design.

Using Quartus Global Signals

# Quartus QSF: promote rst_n to a global signal
set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to rst_n

When to Insert Reset Buffers Manually

Static Timing Analysis (STA) must be correctly configured to handle reset signals. Without proper constraints, the timing tool may either report false violations on the asynchronous reset path or — more dangerously — fail to check the recovery/removal timing altogether.

Verifying Reset Inference in RTL Viewer

SDC Timing Constraints for Asynchronous Reset

# SDC constraints file (.sdc)
# Declare the raw asynchronous reset input as a false path
# The Reset Synchronizer handles the timing; no setup/hold check is needed here
set_false_path -from [get_ports {ext_rst_n}] -to [all_registers]

Checking Recovery and Removal Times

The following errors are common in practice and among the most difficult to diagnose because they often cause intermittent, non-reproducible failures rather than obvious, immediate faults.

// ERROR: rst_n is active-low but is used without inversion
// This module is always in reset when it should be running
always @(posedge clk or negedge rst_n) begin
    if (rst_n)       // Bug: should be (!rst_n)
        q <= 8'h00;
    else
        q <= d;
end

// CORRECT: check the inverted value for active-low reset
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        q <= 8'h00;
    else
        q <= d;
end

// ERROR: raw async reset driven directly into a different clock domain
module domain_b (
    input wire clk_b,
    input wire raw_rst_n,   // This signal is asynchronous to clk_b — DANGEROUS
    output reg q
);
    always @(posedge clk_b or negedge raw_rst_n) begin
        if (!raw_rst_n) q <= 1'b0;
        else            q <= ~q;
    end
endmodule

// CORRECT: pass raw_rst_n through a Reset Synchronizer clocked by clk_b first
// reset_synchronizer u_sync (.clk(clk_b), .async_rst_n(raw_rst_n), .sync_rst_n(rst_n_b));
module domain_b (
    input wire clk_b,
    input wire rst_n_b,     // Synchronized reset — safe to use
    output reg q
);
    always @(posedge clk_b or negedge rst_n_b) begin
        if (!rst_n_b) q <= 1'b0;
        else          q <= ~q;
    end
endmodule

// ERROR: reset check inside combinational always block — infers latch
always @(*) begin
    if (!rst_n)
        y = 8'h00;
    else if (sel)
        y = a;
    // Missing else: latch inferred for the case where rst_n=1 and sel=0
end

// CORRECT: reset belongs in the clocked always block
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        y <= 8'h00;
    else if (sel)
        y <= a;
    else
        y <= b;
end

// ERROR: reset does not initialize the state register
// After reset, 'state' is undefined — FSM behavior is unpredictable
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        output_reg <= 8'h00;   // Data registers cleared, but state is not set
    end else begin
        case (state)
            // ...
        endcase
    end
end

// CORRECT: always initialize the state register explicitly in the reset branch
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        state      <= IDLE;    // FSM enters a defined, valid state after reset
        output_reg <= 8'h00;
    end else begin
        case (state)
            IDLE: // ...
            // ...
        endcase
    end
end

The following table consolidates all reset best practices covered in this section:

The most fundamental register is a single D flip-flop — a one-bit storage element that captures its input on every rising clock edge and holds that value until the next active edge. It is the building block from which all other register patterns are derived.

// Single-bit D flip-flop
// Captures input d on every rising clock edge
module dff_single (
    input  wire clk,
    input  wire d,
    output reg  q
);
    always @(posedge clk) begin
        q <= d;
    end
endmodule

On the Intel MAX-10, this maps directly to one Logic Element (LE) using its embedded flip-flop. The LUT portion of the LE is unused for this pattern.

Typical applications:

A clock enable signal (en) allows the register to selectively ignore clock edges — the flip-flop only captures its input when en = 1. When en = 0, the output holds its current value.

// Register with clock enable
// Captures input d only when en = 1; holds current value when en = 0
module dff_enable (
    input  wire clk,
    input  wire en,    // Clock enable
    input  wire d,
    output reg  q
);
    always @(posedge clk) begin
        if (en)
            q <= d;
        // Implicit else: q retains its value when en = 0
    end
endmodule

Important: Never Gate the Clock Signal Directly

// WRONG: gating the clock with combinational logic
// This creates a glitchy, skewed clock — never do this in FPGA design
wire gated_clk = clk & en;   // Dangerous: combinational glitch on clock

always @(posedge gated_clk) begin
    q <= d;
end

// CORRECT: use a clock enable signal inside the always block
// The flip-flop clock is always the clean system clock
always @(posedge clk) begin
    if (en)
        q <= d;
end

Typical applications:

Combining reset and clock enable produces the most commonly used register pattern in real FPGA designs. The priority ordering is critical: reset must always take precedence over enable. If enable were checked first, a disabled register could not be reset — leaving it in an unknown state after system initialization.

Version A: Asynchronous Reset with Enable (Recommended for Control Logic)

// Full-featured register: asynchronous reset + clock enable
// Priority: reset > enable > hold
module dff_async_rst_en (
    input  wire clk,
    input  wire rst_n,   // Active-low asynchronous reset (highest priority)
    input  wire en,      // Clock enable
    input  wire d,
    output reg  q
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)      // Reset: immediate, unconditional
            q <= 1'b0;
        else if (en)     // Enable: capture data only when enabled
            q <= d;
        // Implicit else: hold current value when en = 0
    end
endmodule

Version B: Synchronous Reset with Enable (Recommended for Datapath Logic)

// Full-featured register: synchronous reset + clock enable
// Priority: reset > enable > hold
module dff_sync_rst_en (
    input  wire clk,
    input  wire rst_n,   // Active-low synchronous reset (highest priority)
    input  wire en,      // Clock enable
    input  wire d,
    output reg  q
);
    always @(posedge clk) begin   // Only clk in sensitivity list
        if (!rst_n)      // Reset: cleared on next clock edge
            q <= 1'b0;
        else if (en)     // Enable: capture data only when enabled
            q <= d;
        // Implicit else: hold current value when en = 0
    end
endmodule

Synthesized hardware structure (asynchronous version):

Typical applications:

A shift register is a chain of flip-flops in which the output of each stage connects to the input of the next. On each clock edge, the stored bit pattern shifts one position along the chain. Shift registers are categorized by their input and output mode — serial or parallel — giving four standard types.

Type 1: SISO — Serial-In Serial-Out

// SISO Shift Register — 8-stage delay line
// Output is the input delayed by 8 clock cycles
module siso_shift_reg #(
    parameter DEPTH = 8
) (
    input  wire clk,
    input  wire rst_n,
    input  wire s_in,    // Serial input
    output wire s_out    // Serial output (delayed by DEPTH cycles)
);
    reg [DEPTH-1:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            shift_reg <= {DEPTH{1'b0}};
        else
            shift_reg <= {shift_reg[DEPTH-2:0], s_in};  // Shift left, insert at LSB
    end

    assign s_out = shift_reg[DEPTH-1];   // Output from MSB (oldest bit)
endmodule

Type 2: SIPO — Serial-In Parallel-Out

// SIPO Shift Register — 8-bit serial receiver
// Converts a serial bit stream into an 8-bit parallel word
module sipo_shift_reg (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       s_in,     // Serial input (LSB first)
    output reg  [7:0] p_out     // Parallel output — full 8-bit word
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            p_out <= 8'h00;
        else
            p_out <= {p_out[6:0], s_in};   // Shift in from LSB
    end
endmodule

Type 3: PISO — Parallel-In Serial-Out

// PISO Shift Register — 8-bit serial transmitter
// Loads an 8-bit parallel word and shifts it out one bit at a time
module piso_shift_reg (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       load,     // 1 = load parallel data; 0 = shift out
    input  wire [7:0] p_in,     // Parallel data input
    output wire       s_out     // Serial output (MSB first)
);
    reg [7:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            shift_reg <= 8'h00;
        else if (load)
            shift_reg <= p_in;              // Load parallel data in one cycle
        else
            shift_reg <= {shift_reg[6:0], 1'b0};  // Shift left, output MSB
    end

    assign s_out = shift_reg[7];   // MSB is transmitted first
endmodule

Type 4: PIPO — Parallel-In Parallel-Out

// PIPO Register — 8-bit pipeline stage register
// Captures all 8 input bits simultaneously on the clock edge
module pipo_register (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       en,       // Clock enable
    input  wire [7:0] d,        // Parallel data input
    output reg  [7:0] q         // Parallel data output
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 8'h00;
        else if (en)
            q <= d;
    end
endmodule

The following table provides a quick reference for all six register patterns covered in this section:

Design rule: always verify the synthesized hardware structure using the RTL Viewer and Technology Map Viewer in Quartus Prime after compilation. Confirm that control signals are mapped to the correct dedicated LE hardware pins (CLR for reset, ENA for clock enable) rather than being absorbed into LUT logic unnecessarily.

This section assumes familiarity with the parameter, localparam, and `define constructs introduced in Lesson 05. The table below provides a brief recap of their key differences for quick reference. For full syntax details and scope rules, refer back to Lesson 05.

The key design rule for this section is:

The first application is to rewrite the full-featured register from Section 10.4.5 as a parameterized module. The data width is exposed as a parameter so that any instantiating module can specify the exact width it needs without modifying the register source file.

// Parameterized N-bit register with asynchronous reset and clock enable
// Default width is 8 bits; override at instantiation as needed
module reg_n #(
    parameter WIDTH     = 8,              // Data width in bits
    parameter RST_VALUE = {WIDTH{1'b0}}   // Reset value — default all zeros
) (
    input  wire             clk,
    input  wire             rst_n,
    input  wire             en,
    input  wire [WIDTH-1:0] d,
    output reg  [WIDTH-1:0] q
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= RST_VALUE;
        else if (en)
            q <= d;
    end
endmodule

This single module replaces every fixed-width register variant from Section 10.4. The width and reset value are both configurable at instantiation time.

Instantiation Examples

// 8-bit register with default reset value (all zeros)
reg_n #(
    .WIDTH     (8),
    .RST_VALUE (8'h00)
) u_data_reg (
    .clk   (clk),
    .rst_n (rst_n),
    .en    (wr_en),
    .d     (data_in),
    .q     (data_out)
);

// 16-bit register with non-zero reset value
reg_n #(
    .WIDTH     (16),
    .RST_VALUE (16'hFFFF)
) u_ctrl_reg (
    .clk   (clk),
    .rst_n (rst_n),
    .en    (ctrl_wr_en),
    .d     (ctrl_in),
    .q     (ctrl_out)
);

// 32-bit register — no source code changes required
reg_n #(
    .WIDTH (32)
) u_acc_reg (
    .clk   (clk),
    .rst_n (rst_n),
    .en    (acc_en),
    .d     (acc_in),
    .q     (acc_out)
);

When a module contains internal constants that are mathematically derived from its parameters, those constants must be computed inside the module using localparam. This guarantees that derived values remain consistent with the primary parameter regardless of the width chosen at instantiation.

A common example is a parameterized shift register where the internal counter that tracks the shift position must be wide enough to count up to DEPTH - 1. The required counter width is $clog2(DEPTH) — the ceiling log base 2 of the depth, which gives the minimum number of bits needed to represent that count.

// Parameterized SISO shift register using localparam for derived width
module siso_n #(
    parameter DEPTH = 8    // Shift register depth (number of pipeline stages)
) (
    input  wire clk,
    input  wire rst_n,
    input  wire s_in,
    output wire s_out
);
    // localparam: derived from DEPTH, cannot be overridden externally
    // $clog2(DEPTH) gives the number of bits needed to index DEPTH stages
    localparam ADDR_W = $clog2(DEPTH);

    reg [DEPTH-1:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            shift_reg <= {DEPTH{1'b0}};
        else
            shift_reg <= {shift_reg[DEPTH-2:0], s_in};
    end

    assign s_out = shift_reg[DEPTH-1];
endmodule

If DEPTH is changed from 8 to 32 at instantiation, ADDR_W automatically recalculates from 3 to 5. No internal constants need to be manually updated.

Common localparam Patterns

// Common localparam derivation patterns used in register and counter design

// Pattern 1: counter bit-width from maximum count value
parameter  MAX_COUNT = 255;
localparam CNT_W     = $clog2(MAX_COUNT + 1);   // 8 bits for 0..255

// Pattern 2: byte count from total bit-width
parameter  DATA_W    = 32;
localparam BYTE_CNT  = DATA_W / 8;              // 4 bytes for 32-bit data

// Pattern 3: FSM state encoding width from number of states
parameter  NUM_STATES = 6;
localparam STATE_W    = $clog2(NUM_STATES);     // 3 bits for 6 states

// Pattern 4: terminal count for a divider counter
parameter  CLK_FREQ   = 50_000_000;
parameter  BAUD_RATE  = 115_200;
localparam DIVIDER    = CLK_FREQ / BAUD_RATE - 1;
localparam DIV_W      = $clog2(DIVIDER + 1);

A register bank consists of multiple independently addressable registers sharing a common clock and reset. Parameterizing both the data width and the number of registers produces a fully reusable memory-mapped register block suitable for peripheral controller designs.

// Parameterized register bank
// NUM_REGS individually addressable registers, each WIDTH bits wide
module reg_bank #(
    parameter WIDTH    = 8,     // Data width of each register
    parameter NUM_REGS = 4      // Number of registers in the bank
) (
    input  wire                       clk,
    input  wire                       rst_n,
    input  wire                       wr_en,              // Write enable
    input  wire [$clog2(NUM_REGS)-1:0] addr,             // Register address
    input  wire [WIDTH-1:0]           wr_data,           // Write data
    output reg  [WIDTH-1:0]           rd_data            // Read data
);
    // localparam: address width derived from number of registers
    localparam ADDR_W = $clog2(NUM_REGS);

    // Register array: NUM_REGS registers, each WIDTH bits wide
    reg [WIDTH-1:0] regs [0:NUM_REGS-1];

    integer i;

    // Write port: synchronous write with asynchronous reset
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            for (i = 0; i < NUM_REGS; i = i + 1)
                regs[i] <= {WIDTH{1'b0}};   // Clear all registers on reset
        end else if (wr_en) begin
            regs[addr] <= wr_data;
        end
    end

    // Read port: combinational (asynchronous) read
    always @(*) begin
        rd_data = regs[addr];
    end

endmodule

Instantiation Example

// 16-bit wide bank of 8 registers — suitable for a simple peripheral CSR block
reg_bank #(
    .WIDTH    (16),
    .NUM_REGS (8)
) u_csr_bank (
    .clk     (clk),
    .rst_n   (rst_n),
    .wr_en   (csr_wr_en),
    .addr    (csr_addr),
    .wr_data (csr_wr_data),
    .rd_data (csr_rd_data)
);

To demonstrate how parameterization applies to the shift register patterns from Section 10.4, the PISO transmitter is rewritten here as a fully parameterized module. Both the data width and the shift direction (MSB-first or LSB-first) are configurable at instantiation.

// Parameterized PISO shift register
// Configurable width and shift direction
// MSB_FIRST = 1: transmit MSB first (SPI default)
// MSB_FIRST = 0: transmit LSB first (UART default)
module piso_n #(
    parameter WIDTH     = 8,   // Data width
    parameter MSB_FIRST = 1    // Shift direction: 1 = MSB first, 0 = LSB first
) (
    input  wire             clk,
    input  wire             rst_n,
    input  wire             load,      // 1 = load parallel data; 0 = shift
    input  wire [WIDTH-1:0] p_in,      // Parallel data input
    output wire             s_out      // Serial output
);
    reg [WIDTH-1:0] shift_reg;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            shift_reg <= {WIDTH{1'b0}};
        else if (load)
            shift_reg <= p_in;
        else begin
            if (MSB_FIRST)
                shift_reg <= {shift_reg[WIDTH-2:0], 1'b0};  // Shift left
            else
                shift_reg <= {1'b0, shift_reg[WIDTH-1:1]};  // Shift right
        end
    end

    assign s_out = MSB_FIRST ? shift_reg[WIDTH-1] : shift_reg[0];

endmodule

Instantiation Examples

// SPI transmitter: 8-bit, MSB first
piso_n #(
    .WIDTH     (8),
    .MSB_FIRST (1)
) u_spi_tx (
    .clk   (clk),
    .rst_n (rst_n),
    .load  (spi_load),
    .p_in  (tx_byte),
    .s_out (mosi)
);

// UART transmitter: 8-bit, LSB first
piso_n #(
    .WIDTH     (8),
    .MSB_FIRST (0)
) u_uart_tx (
    .clk   (clk),
    .rst_n (rst_n),
    .load  (uart_load),
    .p_in  (tx_byte),
    .s_out (tx_serial)
);

The following practices apply to all parameterized modules in FPGA design:

// Example: well-documented parameter declarations with range comments
module reg_n #(
    parameter WIDTH     = 8,             // Data width: 1 to 64 bits
    parameter RST_VALUE = {WIDTH{1'b0}}  // Reset value: must fit within WIDTH bits
) (
    // ...
);
    // Internal consistency check using localparam
    // WIDTH must be at least 1; RST_VALUE is automatically sized
    localparam ZERO = {WIDTH{1'b0}};
    // ...
endmodule

Verilog supports two distinct array declaration styles that are often confused with each other. Understanding the difference is essential for writing correct, synthesizable RTL and for predicting how Quartus Prime will map the declarations to hardware.

Packed Arrays

// Packed array examples
reg [7:0]  data_byte;     // One 8-bit register (8 flip-flops as one unit)
reg [15:0] data_word;     // One 16-bit register
reg [31:0] data_dword;    // One 32-bit register

// Packed array: entire variable assigned at once
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        data_byte <= 8'h00;
    else
        data_byte <= data_in;
end

// Packed array: individual bit access
wire msb = data_byte[7];          // Single bit select
wire [3:0] upper = data_byte[7:4]; // Part select (upper nibble)
wire [3:0] lower = data_byte[3:0]; // Part select (lower nibble)

Unpacked Arrays

// Unpacked array examples
reg        flags [0:7];      // 8 separate 1-bit registers
reg [7:0]  regs  [0:15];    // 16 separate 8-bit registers
reg [31:0] mem   [0:255];   // 256 separate 32-bit registers (register file / RAM)

// Unpacked array: individual element access using an index
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        regs[0] <= 8'h00;       // Reset one specific register
    else if (wr_en)
        regs[addr] <= wr_data;  // Write to register selected by addr
end

// Unpacked array: read access is combinational
assign rd_data = regs[addr];

// Correct: use a for loop to reset all elements of an unpacked array
integer i;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        for (i = 0; i < 16; i = i + 1)
            regs[i] <= 8'h00;   // Reset each register individually
    end else if (wr_en) begin
        regs[addr] <= wr_data;
    end
end

Side-by-Side Comparison

Several Verilog operators are specifically useful when working with multi-bit registers. Understanding these operators allows complex register manipulations to be expressed concisely and synthesized efficiently.

Bit-Select and Part-Select

reg [15:0] status_reg;

// Bit-select: access a single bit by index
wire tx_busy  = status_reg[0];   // Bit 0: TX busy flag
wire rx_ready = status_reg[1];   // Bit 1: RX ready flag
wire error    = status_reg[7];   // Bit 7: error flag

// Part-select: access a contiguous range of bits
wire [3:0] irq_flags  = status_reg[11:8];   // Bits 11..8: interrupt flags
wire [3:0] mode_field = status_reg[15:12];  // Bits 15..12: mode selection

// Part-select on left-hand side: write to a specific field
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        status_reg <= 16'h0000;
    else if (irq_wr_en)
        status_reg[11:8] <= irq_data;   // Update only the IRQ field
end

Concatenation

reg [7:0] high_byte, low_byte;
reg [15:0] combined;

// Concatenation: join two 8-bit registers into one 16-bit register
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        combined <= 16'h0000;
    else
        combined <= {high_byte, low_byte};  // high_byte becomes [15:8], low_byte [7:0]
end

// Concatenation in shift register: insert new bit at LSB, discard MSB
reg [7:0] shift_reg;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        shift_reg <= 8'h00;
    else
        shift_reg <= {shift_reg[6:0], serial_in};  // Shift left, insert at bit 0
end

// Concatenation to swap byte order (endian conversion)
wire [15:0] swapped = {combined[7:0], combined[15:8]};

Replication

// Replication for register initialization
reg [31:0] wide_reg;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        wide_reg <= {32{1'b0}};   // Equivalent to 32'h00000000
    else
        wide_reg <= data_in;
end

// Replication for sign extension: extend an 8-bit signed value to 16 bits
wire [7:0]  signed_byte = 8'hA5;           // 1010_0101 = -91 in two's complement
wire [15:0] sign_extended = {{8{signed_byte[7]}}, signed_byte};
// signed_byte[7] = 1 (negative), so upper 8 bits = 8'hFF
// Result: 16'hFFA5

// Replication in parameterized reset
parameter WIDTH = 16;
reg [WIDTH-1:0] param_reg;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        param_reg <= {WIDTH{1'b0}};   // Works for any WIDTH value
    else
        param_reg <= d;
end

A register array is an unpacked array of multi-bit registers, declared and accessed as described in Section 10.6.1. It forms the basis of any addressable storage structure: configuration register banks, lookup tables, and small on-chip memories.

// Parameterized register array with synchronous write and asynchronous read
// Models a small block of addressable registers (e.g., peripheral CSR block)
module reg_array #(
    parameter DATA_W   = 8,     // Data width of each register
    parameter NUM_REGS = 16,    // Number of registers
    localparam ADDR_W  = $clog2(NUM_REGS)   // Address width
) (
    input  wire                clk,
    input  wire                rst_n,
    // Write port
    input  wire                wr_en,
    input  wire [ADDR_W-1:0]   wr_addr,
    input  wire [DATA_W-1:0]   wr_data,
    // Read port
    input  wire [ADDR_W-1:0]   rd_addr,
    output wire [DATA_W-1:0]   rd_data
);
    // Register array declaration
    reg [DATA_W-1:0] regs [0:NUM_REGS-1];

    integer i;

    // Synchronous write with asynchronous reset
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            for (i = 0; i < NUM_REGS; i = i + 1)
                regs[i] <= {DATA_W{1'b0}};   // Clear all registers on reset
        end else if (wr_en) begin
            regs[wr_addr] <= wr_data;
        end
    end

    // Asynchronous (combinational) read
    assign rd_data = regs[rd_addr];

endmodule

Quartus Synthesis Inference for Register Arrays

A register file is a structured collection of registers with one or more independent read and write ports, designed to be accessed by index (address). It is the central storage element of a processor datapath — the general-purpose registers of a CPU are implemented as a register file. Understanding register file design is therefore a prerequisite for any CPU or ALU implementation in later chapters.

The standard register file configuration for a simple RISC-style datapath has:

// Dual-read, single-write Register File
// Typical use: RISC processor general-purpose register bank
// Register 0 is hardwired to zero (writes to reg 0 are ignored)
module register_file #(
    parameter DATA_W  = 32,    // Data width (e.g., 32-bit RISC architecture)
    parameter NUM_REG = 32,    // Number of registers (e.g., 32 for MIPS/RISC-V)
    localparam ADDR_W = $clog2(NUM_REG)
) (
    input  wire                clk,
    input  wire                rst_n,

    // Write port
    input  wire                wr_en,       // Write enable
    input  wire [ADDR_W-1:0]   wr_addr,     // Write address (destination register)
    input  wire [DATA_W-1:0]   wr_data,     // Write data

    // Read port A (source operand 1, e.g., rs1)
    input  wire [ADDR_W-1:0]   rd_addr_a,
    output wire [DATA_W-1:0]   rd_data_a,

    // Read port B (source operand 2, e.g., rs2)
    input  wire [ADDR_W-1:0]   rd_addr_b,
    output wire [DATA_W-1:0]   rd_data_b
);
    // Register storage array
    reg [DATA_W-1:0] rf [0:NUM_REG-1];

    integer i;

    // Synchronous write port with asynchronous reset
    // Register 0 is never written — it is permanently zero
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            for (i = 0; i < NUM_REG; i = i + 1)
                rf[i] <= {DATA_W{1'b0}};
        end else if (wr_en && (wr_addr != {ADDR_W{1'b0}})) begin
            rf[wr_addr] <= wr_data;   // Write to any register except register 0
        end
    end

    // Asynchronous read ports
    // Register 0 always returns zero regardless of stored value
    assign rd_data_a = (rd_addr_a == {ADDR_W{1'b0}}) ? {DATA_W{1'b0}} : rf[rd_addr_a];
    assign rd_data_b = (rd_addr_b == {ADDR_W{1'b0}}) ? {DATA_W{1'b0}} : rf[rd_addr_b];

endmodule

Read-During-Write Behavior

Mistake 1: Whole-Array Assignment to an Unpacked Array

// ERROR: whole-array assignment — not supported in synthesis
reg [7:0] regs [0:15];
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        regs <= 0;   // Illegal: cannot assign to an unpacked array as a whole
end

// CORRECT: use a for loop to reset each element individually
integer i;
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        for (i = 0; i < 16; i = i + 1)
            regs[i] <= 8'h00;
    end
end

Mistake 2: Out-of-Range Array Index

// Potential issue: addr may be wider than needed, allowing out-of-range access
reg [7:0]  regs [0:15];   // 16 registers, valid index: 0..15
reg [7:0]  addr;          // 8-bit address — can represent 0..255, but only 0..15 are valid

// If addr > 15, behavior is undefined
assign rd_data = regs[addr];   // Risk: addr could be 16..255

// CORRECT: use a localparam-derived address width to prevent over-indexing
localparam NUM_REGS = 16;
localparam ADDR_W   = $clog2(NUM_REGS);  // 4 bits: can represent 0..15 exactly

reg [7:0]          regs [0:NUM_REGS-1];
reg [ADDR_W-1:0]   addr;   // 4-bit address: physically cannot exceed 15

assign rd_data = regs[addr];   // Safe: addr is bounded by its width

Mistake 3: Packed/Unpacked Dimension Confusion

// These two declarations look similar but are completely different:

reg [7:0] A [0:3];   // Unpacked: 4 separate 8-bit registers
                     // Access: A[0], A[1], A[2], A[3]
                     // A[0] = one 8-bit register; A[0][3] = bit 3 of register 0

reg [3:0] B [0:7];   // Unpacked: 8 separate 4-bit registers
                     // Access: B[0]..B[7]
                     // B[0] = one 4-bit register; B[0][3] = MSB of register 0

// DO NOT confuse with:
reg [7:0] C;         // Packed: one single 8-bit register
                     // Access: C[7:0], C[3], C[7:4]
                     // No unpacked dimension — cannot use C[0] as an array index

Mistake 4: Inferring Unintended Block RAM

// Risk of Block RAM inference: both write and read are synchronous
always @(posedge clk) begin
    if (wr_en)
        regs[wr_addr] <= wr_data;
end
always @(posedge clk) begin
    rd_data <= regs[rd_addr];   // Synchronous read — may infer Block RAM
end

// Prevents Block RAM inference: read is asynchronous
always @(posedge clk) begin
    if (wr_en)
        regs[wr_addr] <= wr_data;   // Synchronous write
end
assign rd_data = regs[rd_addr];     // Asynchronous read — infers flip-flops or MLAB

From a hardware perspective, a counter is not a fundamentally new type of circuit — it is a register augmented with a feedback path through combinational arithmetic logic. Every counter consists of exactly three elements:

// The feedback loop is explicit in Verilog:
// count (register output) appears on both the left-hand side (storage)
// and the right-hand side (feedback into adder)
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= {WIDTH{1'b0}};
    else if (en)
        count <= count + 1'b1;   // count feeds back into the adder
        //       ^^^^^
        //       This is the feedback path
end

This feedback loop is clearly visible in the RTL Viewer in Quartus Prime as a wire looping from the register output back to the adder input. Verifying the presence of this loop after synthesis is a reliable way to confirm that the synthesis tool has correctly inferred a counter rather than a combinational function.

Counter vs Register: The Critical Difference

The choice of count encoding determines the hardware cost, switching activity, maximum operating frequency, and suitability for specific applications. Three encodings are relevant to FPGA counter design.

Binary Encoding

Gray Code Encoding

One-Hot Encoding

Encoding Comparison Summary

When a counter reaches its maximum value and increments one more time, the result wraps around. The wrap-around behavior depends on whether the counter uses natural binary overflow or a forced terminal-count reset, and the choice has a direct impact on the amount of logic required.

Natural Wrap-around (Binary Overflow)

// Natural wrap-around: no comparator, just an adder
// 4-bit counter: counts 0, 1, 2, ..., 14, 15, 0, 1, 2, ...
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= 4'b0000;
    else if (en)
        count <= count + 1'b1;   // At 4'b1111 + 1 = 4'b0000 (overflow discarded)
end

Forced Reset (Modulo-N, Non-Power-of-Two)

// Forced reset at terminal count: comparator required
// Modulo-10 counter: counts 0, 1, 2, ..., 9, 0, 1, 2, ...
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
        count <= 4'b0000;
    else if (en) begin
        if (count == 4'd9)       // Comparator: detect terminal count
            count <= 4'b0000;    // Forced reset to zero
        else
            count <= count + 1'b1;
    end
end

Hardware Cost Comparison

The counter is one of the most common sources of critical path violations in FPGA designs. Understanding why, and how Intel MAX-10 mitigates the problem, is essential for designing high-speed counters.

The Critical Path in a Binary Counter

Intel MAX-10 Carry Chain Optimization

Fmax vs Counter Width

The Comparator as an Additional Critical Path Element

// Optimized Modulo-N counter: registered terminal count detection
// tc_reg is registered one cycle before the actual wrap, reducing critical path
module modulo_fast #(
    parameter MODULO = 100,
    localparam WIDTH = $clog2(MODULO)
) (
    input  wire             clk,
    input  wire             rst_n,
    input  wire             en,
    output reg  [WIDTH-1:0] count,
    output reg              tc       // Registered terminal count (one cycle early)
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            count <= {WIDTH{1'b0}};
            tc    <= 1'b0;
        end else if (en) begin
            if (tc) begin
                count <= {WIDTH{1'b0}};   // Reset triggered by registered tc
                tc    <= (MODULO == 1);   // tc stays high only if MODULO = 1
            end else begin
                count <= count + 1'b1;
                tc    <= (count == MODULO - 2);  // Detect terminal-1 one cycle early
            end
        end
    end
endmodule

When a counter wider than 32 bits is required, or when a very large modulus is needed, the design can be split into cascaded stages. The terminal count output of the lower stage drives the enable input of the upper stage, effectively multiplying the count range without creating an excessively long carry chain.

// Cascaded 48-bit counter built from two 24-bit stages
// Lower stage counts 0..2^24-1; upper stage advances once per lower overflow
module counter_48bit (
    input  wire        clk,
    input  wire        rst_n,
    input  wire        en,
    output wire [47:0] count     // Full 48-bit count value
);
    wire [23:0] count_lo, count_hi;
    wire        ovf_lo;           // Overflow of lower 24 bits

    // Lower 24-bit stage: always enabled when en is active
    up_counter #(.WIDTH(24)) u_lo (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (en),
        .count (count_lo),
        .ovf   (ovf_lo)
    );

    // Upper 24-bit stage: advances only when lower stage overflows
    up_counter #(.WIDTH(24)) u_hi (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (ovf_lo),   // Enable from lower stage overflow
        .count (count_hi),
        .ovf   ()          // Upper overflow not used here
    );

    assign count = {count_hi, count_lo};

endmodule

Each stage has its own independent carry chain limited to 24 bits, keeping the critical path short. The enable signal (ovf_lo) between stages is a registered signal (the overflow flag of the lower counter), so it does not add combinational delay to either stage's critical path.

After synthesizing a counter module, four verification steps should be performed before proceeding to integration or lab testing.

Step 1: Confirm Feedback Loop in RTL Viewer

Step 2: Confirm Carry Chain in Technology Map Viewer

Step 3: Check Fmax in Timing Analyzer

Step 4: Simulate Count Sequence in Simulation Waveform Editor

The up counter is the most fundamental sequential circuit in digital design. It increments its stored value by one on every active clock edge and wraps back to zero after reaching its maximum value. The wrap-around occurs naturally due to binary arithmetic overflow — no additional comparison logic is required, making this the most area-efficient counter type.

// Parameterized N-bit Up Counter with asynchronous reset
// Counts from 0 to (2^WIDTH - 1), then wraps back to 0 automatically
module up_counter #(
    parameter WIDTH = 8    // Counter width in bits; range: 1..32
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset
    input  wire             en,      // Count enable
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             ovf      // Overflow flag: pulses high for one cycle at wrap
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (en)
            count <= count + 1'b1;
    end

    // Overflow: asserted when count is at maximum AND enable is active
    assign ovf = en & (&count);   // (&count) = reduction AND = 1 only when all bits are 1
endmodule

Hardware structure:

Typical applications:

The down counter decrements its stored value on every active clock edge. When the count reaches zero, it wraps back to its maximum value through natural binary underflow. A terminal count (TC) flag is commonly added to signal when the counter has reached zero, making it suitable for timeout and delay generation circuits.

// Parameterized N-bit Down Counter with asynchronous reset
// Counts from (2^WIDTH - 1) down to 0, then wraps back to (2^WIDTH - 1)
module down_counter #(
    parameter WIDTH = 8    // Counter width in bits; range: 1..32
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset (loads max value)
    input  wire             en,      // Count enable
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             tc       // Terminal count: high for one cycle when count = 0
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b1}};   // Reset to maximum value (all ones)
        else if (en)
            count <= count - 1'b1;
    end

    // Terminal count: asserted when count is zero AND enable is active
    assign tc = en & ~(|count);   // (|count) = reduction OR = 0 only when all bits are 0
endmodule

Typical applications:

The up/down counter counts in either direction under the control of a direction signal (dir). When dir = 1 the counter increments; when dir = 0 it decrements. Both overflow and underflow wrap around naturally.

// Parameterized N-bit Up/Down Counter with asynchronous reset
// dir = 1: count up; dir = 0: count down
module updown_counter #(
    parameter WIDTH = 8    // Counter width in bits; range: 1..32
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset
    input  wire             en,      // Count enable
    input  wire             dir,     // Direction: 1 = up, 0 = down
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             ovf,     // Overflow:  count was at max and counted up
    output wire             unf      // Underflow: count was at 0 and counted down
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (en) begin
            if (dir)
                count <= count + 1'b1;   // Count up
            else
                count <= count - 1'b1;   // Count down
        end
    end

    // Overflow: counting up from maximum value
    assign ovf = en &  dir & (&count);

    // Underflow: counting down from zero
    assign unf = en & ~dir & ~(|count);

endmodule

Typical applications:

A Modulo-N counter counts from 0 to N-1 and then resets to 0 on the next clock edge. Unlike the natural wrap-around of a binary counter, the terminal value N-1 is arbitrary and does not need to be a power of two minus one. This requires a comparator to detect when the count has reached N-1 and force a synchronous reset to zero on the following cycle.

The Modulo-N counter is one of the most frequently used counters in practical FPGA design because it generates a precisely controlled periodic event every N clock cycles.

// Parameterized Modulo-N Counter with asynchronous reset
// Counts from 0 to (MODULO - 1), then resets to 0
// The terminal count pulse (tc) is asserted for one cycle when count = MODULO - 1
module modulo_counter #(
    parameter MODULO = 10,                        // Count modulus; must be >= 2
    localparam WIDTH = $clog2(MODULO)             // Minimum bit-width for the count
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset
    input  wire             en,      // Count enable
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             tc       // Terminal count: high for one cycle at MODULO-1
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (en) begin
            if (count == MODULO - 1)
                count <= {WIDTH{1'b0}};   // Reset to 0 at terminal count
            else
                count <= count + 1'b1;
        end
    end

    // Terminal count: asserted one cycle before the reset
    assign tc = en & (count == MODULO - 1);
endmodule

Practical Example: Baud Rate Generator Using Modulo-N Counter

// Baud rate generator: 50 MHz system clock, 115200 baud
// MODULO = 50,000,000 / 115,200 = 434 (rounded)
// The baud_tick output pulses high for one cycle every 434 clock cycles
module baud_rate_gen #(
    parameter CLK_FREQ  = 50_000_000,
    parameter BAUD_RATE = 115_200,
    localparam MODULO   = CLK_FREQ / BAUD_RATE,
    localparam WIDTH    = $clog2(MODULO)
) (
    input  wire clk,
    input  wire rst_n,
    output wire baud_tick   // One pulse per baud period
);
    wire [WIDTH-1:0] count;

    modulo_counter #(
        .MODULO (MODULO)
    ) u_baud_cnt (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (1'b1),       // Always counting
        .count (count),
        .tc    (baud_tick)   // tc fires every MODULO cycles = one baud period
    );
endmodule

Typical applications:

A Gray code counter produces a sequence in which only one bit changes between consecutive count values. This property is critical in applications where the counter value is read by logic in a different clock domain — if two or more bits changed simultaneously (as in binary counting), a reader in another domain might sample a transitional value where some bits have already changed and others have not, producing a completely incorrect reading.

The standard implementation counts in binary internally and converts to Gray code at the output. The conversion from binary to Gray code is a simple XOR operation:

// Parameterized Gray Code Counter with asynchronous reset
// Internal binary counter converted to Gray code at the output
// Used primarily for asynchronous FIFO read/write pointer generation
module gray_counter #(
    parameter WIDTH = 4    // Counter width in bits; range: 2..16
) (
    input  wire             clk,
    input  wire             rst_n,    // Active-low asynchronous reset
    input  wire             en,       // Count enable
    output wire [WIDTH-1:0] gray_out  // Gray code output
);
    // Internal binary counter
    reg [WIDTH-1:0] bin_count;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            bin_count <= {WIDTH{1'b0}};
        else if (en)
            bin_count <= bin_count + 1'b1;
    end

    // Binary to Gray code conversion: G[i] = B[i] XOR B[i+1]
    // MSB of Gray code equals MSB of binary
    assign gray_out = bin_count ^ (bin_count >> 1);

endmodule

Gray Code Sequence (4-bit Example)

Typical applications:

A BCD counter counts in decimal — each decade (digit) counts from 0 to 9 and then resets to 0 while generating a carry to the next higher decade. Each decimal digit is represented by a 4-bit binary value, giving a range of 0000 (0) to 1001 (9). The values 1010 (10) through 1111 (15) are illegal in BCD and must never appear.

A multi-digit BCD counter is constructed by cascading single-decade BCD counters, where the terminal count output of one decade drives the enable input of the next.

Single-Decade BCD Counter (0 to 9)

// Single-decade BCD counter: counts 0 to 9, then resets to 0
// tc (terminal count) pulses high when count reaches 9
module bcd_decade (
    input  wire       clk,
    input  wire       rst_n,   // Active-low asynchronous reset
    input  wire       en,      // Count enable (driven by tc of previous decade)
    output reg  [3:0] digit,   // BCD digit output (0 to 9)
    output wire       tc       // Terminal count: high for one cycle when digit = 9
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            digit <= 4'd0;
        else if (en) begin
            if (digit == 4'd9)
                digit <= 4'd0;   // Reset to 0 after reaching 9
            else
                digit <= digit + 4'd1;
        end
    end

    assign tc = en & (digit == 4'd9);
endmodule

Three-Decade BCD Counter (000 to 999)

// Three-decade BCD counter: counts 000 to 999
// Cascaded from three single-decade modules
// digit0 = ones, digit1 = tens, digit2 = hundreds
module bcd_counter_3digit (
    input  wire       clk,
    input  wire       rst_n,
    input  wire       en,
    output wire [3:0] digit2,   // Hundreds digit
    output wire [3:0] digit1,   // Tens digit
    output wire [3:0] digit0,   // Ones digit
    output wire       tc        // Terminal count: high when count = 999
);
    wire tc0, tc1;

    // Ones decade: always enabled when en is active
    bcd_decade u_ones (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (en),
        .digit (digit0),
        .tc    (tc0)
    );

    // Tens decade: enabled only when ones decade reaches 9
    bcd_decade u_tens (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (tc0),    // Carry from ones decade
        .digit (digit1),
        .tc    (tc1)
    );

    // Hundreds decade: enabled only when tens decade reaches 9
    bcd_decade u_hundreds (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (tc1),    // Carry from tens decade
        .digit (digit2),
        .tc    (tc)
    );

endmodule

Typical applications:

Ring and Johnson counters are shift-register-based counters that generate specific non-binary sequences without requiring adder logic. They are included here as optional reference material for designers who encounter them in timing generation or phase control applications.

Ring Counter

// 4-bit Ring Counter
// Sequence: 1000 → 0100 → 0010 → 0001 → 1000 → ...
// Each output bit is active for exactly one clock cycle per period
module ring_counter #(
    parameter WIDTH = 4    // Number of stages; range: 2..16
) (
    input  wire             clk,
    input  wire             rst_n,
    input  wire             en,
    output reg  [WIDTH-1:0] ring    // One-hot ring output
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            ring <= {{WIDTH-1{1'b0}}, 1'b1};   // Initialize with single 1 at LSB
        else if (en)
            ring <= {ring[0], ring[WIDTH-1:1]}; // Rotate right
    end
endmodule

Johnson Counter (Twisted-Ring Counter)

// 4-bit Johnson Counter
// Sequence: 0000 → 0001 → 0011 → 0111 → 1111 → 1110 → 1100 → 1000 → 0000 → ...
// 2N = 8 unique states for N = 4
module johnson_counter #(
    parameter WIDTH = 4    // Number of stages; produces 2*WIDTH unique states
) (
    input  wire             clk,
    input  wire             rst_n,
    input  wire             en,
    output reg  [WIDTH-1:0] johnson
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            johnson <= {WIDTH{1'b0}};
        else if (en)
            johnson <= {~johnson[0], johnson[WIDTH-1:1]};  // Feedback inverted LSB to MSB
    end
endmodule

Typical applications:

The following table summarizes the key characteristics of each counter type to guide design decisions:

When multiple control signals are asserted simultaneously, the counter must apply them in a strictly defined priority order. This ordering is not a matter of convention — it has a concrete hardware justification. The priority from highest to lowest is:

In Verilog, this priority ordering is expressed directly as a cascaded if / else if chain inside the always block. The first branch checked has the highest priority:

// Priority template for a fully controlled counter
always @(posedge clk or negedge rst_n) begin
    if (!rst_n)          // Priority 1: reset (unconditional)
        count <= RESET_VAL;
    else if (load)       // Priority 2: load preset value
        count <= preset;
    else if (en)         // Priority 3: count
        count <= count + 1'b1;
    // Implicit else: hold current value (priority 4)
end

The synchronous reset + enable counter is the standard choice for datapath counters where the reset event is always aligned with the system clock — such as baud rate generators, PWM period counters, and pipeline cycle counters.

// Parameterized Up Counter — synchronous reset + clock enable
// Suitable for datapath applications (baud rate, PWM, pipeline timing)
module counter_sync_rst #(
    parameter WIDTH = 8    // Counter width in bits
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low synchronous reset
    input  wire             en,      // Clock enable
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             ovf      // Overflow: count reached maximum
);
    always @(posedge clk) begin      // Synchronous: only clk in sensitivity list
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (en)
            count <= count + 1'b1;
    end

    assign ovf = en & (&count);
endmodule

Synthesized hardware structure:

Typical applications:

The asynchronous reset + enable counter is the standard choice for control logic counters where the reset must take effect immediately — independent of the clock — such as timeout detectors, watchdog counters, and protocol retry counters.

// Parameterized Up Counter — asynchronous reset + clock enable
// Suitable for control logic (timeout, watchdog, protocol retry counter)
module counter_async_rst #(
    parameter WIDTH = 8    // Counter width in bits
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset
    input  wire             en,      // Clock enable
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             ovf      // Overflow: count reached maximum
);
    always @(posedge clk or negedge rst_n) begin   // rst_n in sensitivity list
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (en)
            count <= count + 1'b1;
    end

    assign ovf = en & (&count);
endmodule

Synthesized hardware structure:

Typical applications:

A loadable counter adds a load control signal that forces the counter to a user-specified preset value on the next active clock edge. This makes the counter's starting point configurable at runtime — an essential feature for programmable timers, adjustable PWM duty cycles, and variable-rate event generators.

// Parameterized Loadable Up Counter — asynchronous reset + load + enable
// Priority: reset > load > enable > hold
module counter_loadable #(
    parameter WIDTH = 8    // Counter width in bits
) (
    input  wire             clk,
    input  wire             rst_n,   // Active-low asynchronous reset
    input  wire             load,    // Load preset value (priority 2)
    input  wire             en,      // Count enable (priority 3)
    input  wire [WIDTH-1:0] preset,  // Value to load when load = 1
    output reg  [WIDTH-1:0] count,   // Current count value
    output wire             tc       // Terminal count: count = all ones
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b0}};   // Reset overrides everything
        else if (load)
            count <= preset;          // Load overrides counting
        else if (en)
            count <= count + 1'b1;    // Count when enabled
        // Implicit else: hold current value
    end

    assign tc = en & (&count);
endmodule

Typical applications:

The following module integrates all control signals into a single, fully parameterized counter suitable for direct use in course lab work and project designs. It combines asynchronous reset, clock enable, synchronous load, and bidirectional counting, with a complete set of status outputs.

// Production-Ready Parameterized Counter
// Supports: asynchronous reset, clock enable, synchronous load, up/down direction
// Priority: rst_n (async) > load > en > hold
// Status outputs: overflow, underflow, terminal count
module counter_full #(
    parameter WIDTH     = 8,              // Counter width in bits
    parameter RST_VALUE = {WIDTH{1'b0}}   // Reset value (default: all zeros)
) (
    input  wire             clk,
    input  wire             rst_n,    // Active-low asynchronous reset
    input  wire             en,       // Clock enable
    input  wire             load,     // Synchronous load (overrides counting)
    input  wire             dir,      // Count direction: 1 = up, 0 = down
    input  wire [WIDTH-1:0] preset,   // Preset value loaded when load = 1
    output reg  [WIDTH-1:0] count,    // Current count value
    output wire             ovf,      // Overflow:  counting up   from all-ones
    output wire             unf,      // Underflow: counting down from all-zeros
    output wire             tc_up,    // Terminal count up:   count = all-ones
    output wire             tc_down   // Terminal count down: count = all-zeros
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= RST_VALUE;       // Priority 1: async reset
        else if (load)
            count <= preset;          // Priority 2: synchronous load
        else if (en) begin
            if (dir)
                count <= count + 1'b1;  // Priority 3a: count up
            else
                count <= count - 1'b1;  // Priority 3b: count down
        end
        // Implicit priority 4: hold (en = 0, load = 0, no reset)
    end

    // Status outputs (combinational)
    assign tc_up   =  (&count);                  // All bits = 1
    assign tc_down = ~(|count);                  // All bits = 0
    assign ovf     = en &  dir & tc_up;          // Up overflow
    assign unf     = en & ~dir & tc_down;        // Down underflow

endmodule

Port Description

A programmable hardware timer is one of the most common peripheral modules in embedded FPGA designs. It allows software or higher-level logic to set a timeout period in clock cycles and receive a flag when that period has elapsed. The following implementation uses the counter_loadable module from Section 10.9.4 as its core counting element.

// Programmable Hardware Timer
// Operation:
//   1. Set period_val to the desired timeout in clock cycles minus 1
//   2. Assert start to begin timing (internally loads period_val and enables counter)
//   3. expired pulses high for one clock cycle when the countdown reaches zero
//   4. The timer automatically reloads and restarts if auto_reload = 1
//   5. Assert rst_n low at any time to immediately cancel and reset the timer
module hw_timer #(
    parameter WIDTH = 16   // Timer width; max timeout = 2^WIDTH - 1 clock cycles
) (
    input  wire             clk,
    input  wire             rst_n,       // Active-low asynchronous reset
    input  wire             start,       // Start / restart the timer
    input  wire             auto_reload, // 1 = restart automatically on expiry
    input  wire [WIDTH-1:0] period_val,  // Timeout period in clock cycles (minus 1)
    output wire             running,     // High while timer is active
    output wire             expired      // Pulses high for one cycle on timeout
);
    reg  [WIDTH-1:0] count;
    reg              active;
    wire             tc;

    // Active flag: set by start, cleared on expiry (unless auto_reload)
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            active <= 1'b0;
        else if (start)
            active <= 1'b1;
        else if (tc && !auto_reload)
            active <= 1'b0;   // Stop after one period if auto_reload is off
    end

    // Countdown counter: loads period_val on start or auto-reload expiry
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= {WIDTH{1'b0}};
        else if (start || (tc && auto_reload))
            count <= period_val;          // Load period on start or auto-reload
        else if (active)
            count <= count - 1'b1;        // Count down while active
    end

    // Terminal count: counter has reached zero
    assign tc      = active & ~(|count);
    assign expired = tc;
    assign running = active;

endmodule

Usage Example

// Instantiate a 1-second one-shot timer on a 50 MHz system clock
// period_val = 50,000,000 - 1 = 49,999,999 clock cycles
hw_timer #(
    .WIDTH (26)   // $clog2(50_000_000) = 26 bits required
) u_1sec_timer (
    .clk         (clk),
    .rst_n       (rst_n),
    .start       (timer_start),
    .auto_reload (1'b0),                    // One-shot: stop after one period
    .period_val  (26'd49_999_999),          // 1 second at 50 MHz
    .running     (timer_running),
    .expired     (timer_expired)
);

// Instantiate a 1 kHz auto-reload periodic timer (1 ms period)
// period_val = 50,000 - 1 = 49,999 clock cycles
hw_timer #(
    .WIDTH (16)   // $clog2(50_000) = 16 bits required
) u_1ms_timer (
    .clk         (clk),
    .rst_n       (rst_n),
    .start       (1'b1),                    // Always running
    .auto_reload (1'b1),                    // Periodic: restart automatically
    .period_val  (16'd49_999),              // 1 ms at 50 MHz
    .running     (),                        // Not used
    .expired     (tick_1ms)                 // 1 kHz tick output
);

Synthesis and simulation serve different purposes and are not interchangeable verification methods. A design that compiles without errors in Quartus Prime is not necessarily correct — it only means the RTL is syntactically valid and structurally mappable to hardware. Simulation is the only way to verify that the logic behaves as intended before committing to hardware.

What Simulation Verifies

Simulation-Synthesis Mismatch

A testbench is a non-synthesizable Verilog module that instantiates the design under test (DUT), drives its inputs, and optionally checks its outputs. For the register and counter modules in this chapter, the standard testbench structure consists of four sections: clock generation, reset sequence, stimulus application, and waveform dump.

// Standard Testbench Template for Chapter 10 Register and Counter Modules
// Replace  and port connections to adapt for any DUT
`timescale 1ns / 1ps   // Time unit: 1 ns; time precision: 1 ps

module tb_template;

    // -----------------------------------------------------------------------
    // 1. Signal declarations (mirror the DUT port list)
    // -----------------------------------------------------------------------
    reg         clk;
    reg         rst_n;
    reg         en;
    // Add additional DUT input signals here

    wire [7:0]  count;    // DUT output signals declared as wire
    wire        ovf;

    // -----------------------------------------------------------------------
    // 2. DUT instantiation
    // -----------------------------------------------------------------------
    // Replace with the actual module name and correct port connections
    counter_async_rst #(
        .WIDTH (8)
    ) u_dut (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (en),
        .count (count),
        .ovf   (ovf)
    );

    // -----------------------------------------------------------------------
    // 3. Clock generation: 50 MHz (period = 20 ns)
    // -----------------------------------------------------------------------
    initial clk = 1'b0;
    always #10 clk = ~clk;   // Toggle every 10 ns -> 20 ns period -> 50 MHz

    // -----------------------------------------------------------------------
    // 4. Waveform dump for GTKWave
    // -----------------------------------------------------------------------
    initial begin
        $dumpfile("tb_template.vcd");   // Output VCD file name
        $dumpvars(0, tb_template);      // Dump all signals in this testbench
    end

    // -----------------------------------------------------------------------
    // 5. Stimulus: reset sequence followed by functional tests
    // -----------------------------------------------------------------------
    initial begin
        // Apply asynchronous reset for 3 clock cycles
        rst_n = 1'b0;
        en    = 1'b0;
        #35;            // Hold reset for 35 ns (just past 1.5 clock edges)
        rst_n = 1'b1;   // Release reset
        #20;            // Wait one full clock cycle before applying stimulus

        // --- Functional test stimulus goes here ---
        en = 1'b1;
        #200;           // Count for 10 clock cycles (10 x 20 ns)

        en = 1'b0;
        #40;            // Hold for 2 cycles to verify hold behavior

        en = 1'b1;
        #400;           // Continue counting

        // End simulation
        #20;
        $finish;
    end

endmodule

Key points in this template:

The following testbench targets the dff_async_rst_en module from Section 10.4.5. It verifies reset priority, enable behavior, and the hold state in sequence.

`timescale 1ns / 1ps

module tb_dff_async_rst_en;

    reg        clk, rst_n, en;
    reg        d;
    wire       q;

    // DUT instantiation
    dff_async_rst_en u_dut (
        .clk   (clk),
        .rst_n (rst_n),
        .en    (en),
        .d     (d),
        .q     (q)
    );

    // 50 MHz clock
    initial clk = 0;
    always #10 clk = ~clk;

    // Waveform dump
    initial begin
        $dumpfile("tb_dff_async_rst_en.vcd");
        $dumpvars(0, tb_dff_async_rst_en);
    end

    initial begin
        // --- Phase 1: Power-on reset ---
        rst_n = 0; en = 0; d = 0;
        #35;
        rst_n = 1;
        #20;

        // --- Phase 2: Verify enable = 1, d = 1 -> q should capture 1 ---
        en = 1; d = 1;
        #20;   // One clock cycle
        // Expected: q = 1

        // --- Phase 3: Verify enable = 0 -> q should hold ---
        en = 0; d = 0;
        #40;   // Two clock cycles
        // Expected: q remains 1 (hold, not capturing d = 0)

        // --- Phase 4: Verify enable = 1, d = 0 -> q should capture 0 ---
        en = 1;
        #20;
        // Expected: q = 0

        // --- Phase 5: Verify async reset priority over enable ---
        en = 1; d = 1;
        #20;   // Capture d = 1 -> q = 1
        rst_n = 0;   // Assert reset mid-cycle (not on clock edge)
        #5;          // 5 ns later: q should already be 0 (async, no clock needed)
        rst_n = 1;
        #15;
        // Expected: q went to 0 immediately after rst_n asserted,
        //           without waiting for the next clock edge

        // --- Phase 6: Normal operation after reset release ---
        en = 1; d = 1;
        #20;
        // Expected: q = 1

        #20;
        $finish;
    end

endmodule

Expected GTKWave Waveform Behavior

The following testbench targets the counter_full module from Section 10.9.5. It systematically exercises all control signal combinations and boundary conditions.

`timescale 1ns / 1ps

module tb_counter_full;

    // Parameters matching the DUT
    localparam WIDTH = 4;   // Use 4-bit width for readable waveform

    reg                  clk, rst_n, en, load, dir;
    reg  [WIDTH-1:0]     preset;
    wire [WIDTH-1:0]     count;
    wire                 ovf, unf, tc_up, tc_down;

    // DUT instantiation
    counter_full #(
        .WIDTH     (WIDTH),
        .RST_VALUE ({WIDTH{1'b0}})
    ) u_dut (
        .clk     (clk),
        .rst_n   (rst_n),
        .en      (en),
        .load    (load),
        .dir     (dir),
        .preset  (preset),
        .count   (count),
        .ovf     (ovf),
        .unf     (unf),
        .tc_up   (tc_up),
        .tc_down (tc_down)
    );

    // 50 MHz clock
    initial clk = 0;
    always #10 clk = ~clk;

    // Waveform dump
    initial begin
        $dumpfile("tb_counter_full.vcd");
        $dumpvars(0, tb_counter_full);
    end

    initial begin
        // ---------------------------------------------------------------
        // Phase 1: Power-on async reset
        // ---------------------------------------------------------------
        rst_n = 0; en = 0; load = 0; dir = 1; preset = 0;
        #35;
        rst_n = 1;
        #20;
        // Expected: count = 0 after reset

        // ---------------------------------------------------------------
        // Phase 2: Count up — verify basic increment and tc_up flag
        // ---------------------------------------------------------------
        en = 1; dir = 1;
        #(20 * 16);  // Count through all 16 values (0..15 for 4-bit)
        // Expected: count cycles 0 -> 1 -> ... -> 15 -> 0
        // ovf pulses high for one cycle when count was 15 and incremented

        // ---------------------------------------------------------------
        // Phase 3: Disable counting — verify hold behavior
        // ---------------------------------------------------------------
        en = 0;
        #60;   // 3 clock cycles
        // Expected: count does not change

        // ---------------------------------------------------------------
        // Phase 4: Load preset value — verify load priority over enable
        // ---------------------------------------------------------------
        en = 1; load = 1; preset = 4'd10;
        #20;   // One clock cycle
        load = 0;
        // Expected: count = 10 on the cycle after load is asserted

        // ---------------------------------------------------------------
        // Phase 5: Count down from loaded value — verify unf flag
        // ---------------------------------------------------------------
        dir = 0;   // Count down
        #(20 * 12);
        // Expected: count decrements 10 -> 9 -> ... -> 0
        // unf pulses high when count was 0 and decremented (wraps to 15)

        // ---------------------------------------------------------------
        // Phase 6: Verify reset priority over load
        // ---------------------------------------------------------------
        load = 1; preset = 4'd7;
        #5;      // Mid-cycle: assert reset while load is active
        rst_n = 0;
        #5;
        // Expected: count immediately goes to 0 (reset wins over load)
        rst_n = 1; load = 0;
        #20;

        // ---------------------------------------------------------------
        // Phase 7: Verify reset priority over enable + counting
        // ---------------------------------------------------------------
        en = 1; dir = 1;
        #40;           // Count up for 2 cycles
        rst_n = 0;     // Assert async reset mid-cycle
        #5;
        // Expected: count immediately clears to 0 without waiting for clock
        rst_n = 1;
        #20;

        // ---------------------------------------------------------------
        // Phase 8: Verify simultaneous load and enable (load has priority)
        // ---------------------------------------------------------------
        en = 1; load = 1; preset = 4'd5; dir = 1;
        #20;
        load = 0;
        // Expected: count = 5 (load wins over enable; counter does not increment)
        #40;
        // Expected: count increments from 5

        #20;
        $finish;
    end

endmodule

Simulation Test Coverage Summary

The following commands compile and simulate the counter testbench using Icarus Verilog in the course Jupyter environment. The same pattern applies to any module in this chapter — replace the filenames as needed.

// Step 1: Compile the DUT and testbench together
// iverilog -o    [additional_files]
iverilog -o sim_counter counter_full.v tb_counter_full.v

// Step 2: Run the simulation (generates the .vcd waveform file)
vvp sim_counter

// Step 3: Open the waveform in GTKWave
gtkwave tb_counter_full.vcd &

In the Jupyter notebook environment used in this course, wrap the commands in conda run to ensure the correct environment is active:

// Jupyter notebook cell: compile and simulate using the course conda environment
import subprocess

subprocess.run([
    "conda", "run", "-n", "py312_vsc_base",
    "iverilog", "-o", "sim_counter", "counter_full.v", "tb_counter_full.v"
], check=True)

subprocess.run([
    "conda", "run", "-n", "py312_vsc_base",
    "vvp", "sim_counter"
], check=True)

// GTKWave is launched separately from the desktop environment

After opening the VCD file in GTKWave, add all relevant signals to the waveform view and apply the following interpretation techniques specific to register and counter verification.

Identifying Clock Edge Alignment

Verifying Asynchronous Reset

Verifying Enable Hold Behavior

Measuring Counter Period and Terminal Count Pulse Width

Common Waveform Anomalies and Their Causes

Apply the following checklist to every register and counter module before proceeding to synthesis or board testing. Each item must be confirmed in the GTKWave waveform.