Serial Peripheral Interface Bus (SPI)

The Serial Peripheral Interface bus (SPI) is a synchronous serial communication interface specification used for short-distance communication, primarily in embedded systems. The SPI bus is commonly used for communication with flash memory, sensors, real-time clocks (RTCs), analog-to-digital converters, and modes.

Interface and Features

SPI features include:

  • SPI signals include:
    • SCLK: Serial Clock (output from master)
    • MOSI: Master Output Slave Input (data output from master)
    • MISO: Master Input Slave Output (data output from slave)
    • /SS: Slave Select (often active low, output from master)
    • SDAT: Serial Data I/O (bidirectional I/O, combined MOSI and MISO signals together)
  • Data length: 3- to 16-bit data width
  • Bit rate: support up to 18 Mbps
  • SPI serial bus can be configured as 4-wire (default) and 3-wire mode

SPI Operating Modes

SPI has no pre-defined protocol, so the master and slave must agree on the data frame for the exchange. The data frame is described by clock polarity (CPOL) and clock phase (CPHA). The CPOL parameter defines whether the clock is idle when high or low. CPHA parameter is used to shift the sampling phase. If CPHA = 0, the data will be sampled on the leading (first) clock edge. If CPHA = 1, the data are sampled on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. The 4 modes combine polarity and phase according to the following table:

Table: SPI Clock Phase (CPHA) and Clock Polarity (CPOL) Operation

Mode Clock Polarity
(CPOL)		 Clock Phase
(CPHA)		 SCLK Transmit Edge SCLK Receive Edge SCLK Idle State
0 0 0 Falling Rising Low
1 0 1 Rising Falling Low
2 1 0 Rising Falling High
3 1 1 Falling Rising High

CPOL: used for clock idle state

  • 0 — Clock idle low level
  • 1 — Clock idle high level

CPHA: used to shift the sampling phase

  • 0 — Data Sampled at the leading edge (no delay)
  • 1 — Data Sampled at the trailing edge (delay)

Timing Diagram for Clock Polarity and Phase

The following diagram shows these parameters' four possible states and the SPI mode.

SPI Modes

  • Mode 0 — CPOL = 0, CHPA = 0
    SPI Mode0 s
    Data is sampled at the leading rising edge of the clock. The data must be available before the first clock signal rises. The clock idle state is low (0). The data on MOSI and MISO lines must be stable while the clock is high and can be changed when the clock is low. The data is captured on the clock's rising transition and propagated on the falling clock transition. Mode 0 is the most common mode for SPI bus slave communication.
  • Mode 1 — CPOL = 0, CHPA = 1
    SPI Mode0 s
    Data is sampled at the trailing falling edge of the clock. The first clock signal rising can be used to prepare the data. The clock idle state is low (0). The data on MOSI and MISO lines must be stable while the clock is low and can be changed when the clock is high. The data is captured on the clock's falling transactions and propagated on rising clock transactions.
  • Mode 2 — CPOL = 1, CHPA = 0
    SPI Mode0 s
    Data is sampled at the leading falling edge of the clock. The data must be available before the first clock signal falls. The clock idle state is high (1). The data on MOSI and MISO lines must be stable while the clock is low and can be changed when the clock is high. The data is captured on the clock's falling transition and propagated on the rising clock transition.
  • Mode 3 — CPOL = 1, CHPA = 1
    SPI Mode0 s
    Data is sampled at the trailing rising edge of the clock. The first clock signal falling can be used to prepare the data. The clock's idle state is one. The data on MISO and MOSI lines must be stable while the clock is high and can be changed when the clock is low. The data is captured on the clock's rising transition and propagated on the falling clock transition.

SPI Bus Connection Modes

SPI bus connection can be configured on 4-wire or 3-wire mode.

  • 4-wire serial bus mode: SCLK, MOSI, MISO, AND SS signals

SPI 4WireMode s

  • 3-wire serial bus mode: SCLK, SDAT, and SS signals

SPI 3WireMode s

4-wire bus mode is SPI standard connection mode. It supports full-duplex data transactions, which means SPI allows to transmit and receive data simultaneously on two data lines (MOSI and MISO),

In 3-wire serial bus mode, MOSI and MISO lines are combined into a single bidirectional data line (SDAT). Transactions are half-duplex to allow for bidirectional communication. Reducing the number of data lines and operating in half-duplex mode also decreases the maximum possible throughput; many 3-wire devices have low-performance requirements and are instead designed with low pin count in mind.

SPI Connections for Multiple Slaves

SPI devices communicate in full-duplex mode using a master-slave architecture with a signal master. There are two ways to connect multiple slaves with a master:

Individual Slave Select Configuration

In this configuration, the SCLK, MOSI, and MISO are shared by all devices. Each device has an individual slave select (/SS) line. The master will pull low on a slave /SS line to choose a device for communication. A pull-up resistor on the /SS line is highly recommended for each device to reduce cross-talk between devices. The data lines (MOSI and MISO) are connected with slaves in parallel connections.

SSI Connection01

Daisy Chain Configuration

SPI devices may be connected in a daisy chain configuration. The data lines (MOSI and MISO) are connected with slaves in serial connection — the first slave data output is connected to the second slave data input, etc. The whole chain acts as a communication shift register; daily chaining is often done with shift registers to provide a block of inputs or outputs through SPI. This configuration only requires a single /SS line from the master rather than a separate /SS line for each slave.

SSI Connection02

To write code for a new SPI device, you need to note a few things:

  • What is the maximum SPI clock speed the device can use?
  • Is data first shifted in the Most Significant bit (MSb) or Least Significant bit (LSb)?
  • Is the data clock idle when high or low? Are samples on the rising or falling edge of clock pulses?
  • Is the connection in 4-wire or 3-wire mode?

Reference:

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